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LCD12864(st7920)
整理的网上关于LCD12864(ST7920控制器)的串并口程序,已在stc89c52rd+11.0592MHz的情况下测试通过(Finishing line on LCD12864 (ST7920 controller) serial and parallel programs, in the case of stc89c52rd+11.0592 MHz test)
- 2020-09-13 08:48:00下载
- 积分:1
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exp_rom
通过MATLAB产生单脉冲信号的数据,存储下来作为verilog代码实现的DDS的数据源,用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)
- 2020-06-23 04:40:02下载
- 积分:1
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用VHDL实现十六位移位乘法器 才有移位相加法来实现
用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
- 2022-04-17 17:23:11下载
- 积分:1
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这个是vhdl的彩灯实例程序,里面涵盖了48种的彩灯变化,通过了maxplus的验证,并且在机上实验通过...
这个是vhdl的彩灯实例程序,里面涵盖了48种的彩灯变化,通过了maxplus的验证,并且在机上实验通过-this is the Lantern example VHDL procedures inside covers 48 species of Carnival changes adopted maxplus certification, and the plane through experiments
- 2022-02-28 15:42:23下载
- 积分:1
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DDSN
quartus II 13.0 DDS工程文件,采用VHDL编写,可输出正交两路正弦信号。可以直接用modelsim-alter 仿真(quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter)
- 2021-03-20 16:49:17下载
- 积分:1
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tAtan2Cordic
是codic算法实现atan的C程序,包括定点和浮点程序,已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)
- 2021-02-04 09:59:58下载
- 积分:1
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FPGA——IP_RAM实验
说明: FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-04-08 04:33:51下载
- 积分:1
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Uart2Sdram2TFT_sobel
说明: 使用FPGA实现sobel边缘检测的图像处理算法,更改后可直接使用在自己的系统上。(FPGA is used to implement the image processing algorithm of Sobel edge detection, which can be directly used in its own system after change.)
- 2019-12-30 19:40:45下载
- 积分:1
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频率计
说明: 1、能正确显示输入信号频率;
2、测量频率范围为1Hz ~ 999999Hz;
3、测量结果以十进制数字显示;
4、能测量幅值较小的信号频率;
5、有自动刷新输出数据的功能(如5s刷新一次);
6、有自检模块(如产生100Hz的校准方波);(1. It can correctly display the input signal frequency;
2. The frequency range of measurement is 1Hz ~ 99999hz;
3. The measurement results are displayed in decimal;
4. It can measure signal frequency with small amplitude;
5. It has the function of automatically refreshing the output data (e.g. once in 5S);
6. Self checking module (such as generating 100Hz calibration square wave);)
- 2020-03-28 16:37:56下载
- 积分:1