步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

ByteBlasterII 下载线的制作-Download ByteBlasterII production line

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

说明：  该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)

基于VHDL语言的七段显示管程序， 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)

AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)

rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

代码来源http://www.spacewire.co.uk/video.html，需要CRT显示ITU.656格式的视频的可以参考

自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)