Verilog 编写的IP核，512K的16位SRAM

说明：  秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)

此为实现第14.7.9章所需的激励文件 该代码为门级RTL描述。(Stimulus file to verify Section 14.7.9 the functionality of gate vs. RTL description.)

说明：  一个完整的雷达系统仿真MATLAB程序，非常具有参考价值(A complete radar system simulation MATLAB programs have great reference value)

说明：  模糊控制器verilog程序，模糊控制器最简单的实现方法是将一系列模糊控制规则离线转化为一个查询表（又称为控制表）。这种模糊控制其结构简单，使用方便，是最基本的一种形式。(Verilog program of fuzzy controller)

Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)

采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)

数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;

FIFO的源代码，对FIFO设计有帮助，有借鉴意义，帮助学习VHDL编程(FIFO of the source code, on the FIFO design help, there is reference to help learn VHDL programming)

运用vhdl程序设计语言进行ppm设计，ppm 设计在vhdl语言中非常常用，运用已经越来越广泛。-use vhdl program design language ppm design, vhdl ppm design in a very common language, has become increasingly widespread use.

说明：  可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)