Verilog 编写的IP核，512K的16位SRAM

说明：  Verilog代码实现四分屏，在Vivado平台下实现的，可仿真(Verilog code realizes four screens, which can be simulated under vivado platform)

Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver

基于SDRAM的PCI采集,上位机为VC编写，桥芯片为PLX9054，项目已经做完，上传5个例程，已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)

AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)

程序设置了fpga 的 5x5点阵驱动程序，代码相对比较简洁，这个程序可以作为fpga输出控制，驱动稳压芯片工作，进而点灯

用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。(The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.)

mc8051 很好的学习资料 官网的绝对权威-mc8051 a good learning materials in absolute authority of the official website

用verilog编写的科斯塔斯环，希望有帮助(Costas loop written in verilog helpful)

flv的vhdl教学文件:在线调试 自己慢慢欣赏吧-flv file of VHDL Teaching: Online debug their慢慢欣赏吧

Complete Successive approximation Analog to digital converter along with the source code