Verilog 编写的IP核，512K的16位SRAM

RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference

基于Verilog的数码管模拟扫描程序，分为两种显示方式，一种是数码管逐个显示，另一个是所有数码管一起显示。-Verilog-based digital control analog scanning procedures, two types of display, a digital control-by-show, and the other is with all digital tube display.

verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^

支持{addu、subu、lui、ori、jal、jr、lw、sw、nop}指令集的单周期CPU，verilog硬件描述语言实现(Support {addu, subu, lui, ori, jal, jr, lw, sw, nop} instruction set of one-cycle CPU, Verilog hardware description language implementation)

全加器的VHDL程序实现及仿真-full adder VHDL simulation program and

VHDL Design of BCD to 7-segment decoder using PROM

使用Verilog编写的ad9826的控制模块(the module of ad9826 with verilog)

用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)

参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )

pid程序,新学者，使用FPGA学习，希望大家一起学习