-
Traffic-lights-at-the-crossroads
一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)
- 2013-05-16 10:18:38下载
- 积分:1
-
VHDL source VHDL source VHDL source
VHDL源码 VHDL源码 -VHDL source VHDL source VHDL source
- 2022-01-26 18:08:58下载
- 积分:1
-
ix746
Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.
- 2017-08-28 20:46:28下载
- 积分:1
-
实现大型LED屏显示的CPLD程序,对FPGA学习很有帮助
实现大型LED屏显示的CPLD程序,对FPGA学习很有帮助-To achieve large-scale LED screen display of the CPLD program, very helpful for learning FPGA
- 2022-12-04 07:00:04下载
- 积分:1
-
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分:1
-
rs_encoder
适应多个模式的rs编码,Verilog,选择对应的多项式(RS coding adapted to multiple modes.)
- 2020-06-16 04:40:02下载
- 积分:1
-
CPUver2
这是一个有关单周期CPU设计的一个参考,里面顶层模块已经写好,而其他模块的内容则是以注释的形式存在,如果要跑这个代码的话,把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。(
翻译关闭即时翻译
英语
中文
德语
检测语言
中文(简体)
英语
日语
这是一个有关单周期CPU设计的一个参考,里面顶层模块已经写好,而其他模块的内容则是以注释的形式存在,如果要跑这个代码的话,把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。
This is a reference about a single cycle CPU design, top-level module which has been written, and the contents of the other modules exist in the form of comments, if run this code, those codes include the commented out and then each module is uncommented to commented code.)
- 2016-05-15 15:59:07下载
- 积分:1
-
cpld 控制 8
cpld 控制 8-32M sdram 控制器 maxII epm570实现。
pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation
- 2022-01-26 06:46:28下载
- 积分:1
-
and VHDL source code
VHDL与源代码包-and VHDL source code
- 2022-07-21 05:42:10下载
- 积分:1
-
pdf
说明: 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA,包
括:步骤一、计算重构矩阵;步骤二、重构方位向
多通道数据,包括:步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零,并进行方位向傅里
叶变换;步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘,得到重构完成的方位向数据;(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分:1