应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发...

说明：  Verilog实现的加减法功能计数器，通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)

VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)

Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.

Quartus II软件设计数字电子钟，使用verilog语言编写各个 模块生成symbol files，再用原理图方式制作顶层文件。 完成的功能有：能够显示时、分、秒；具有清零，调节分钟的功能； 具有整点报时功能，声响电路发出叫声； (failed to translate)

pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.

PCIe demo sample code

用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine

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这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)