应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发...

DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under

基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)

基于NiosII系统的可以在DE2-115板子上运行的吞食蛇游戏！（可以使用RS2键盘进行控制）(DE2-115 board NiosII system swallowed snake game! , (RS2 keyboard control))

手机号码归属地查询,代码详尽，简单易懂，欢迎使用！-hello!welcome to my code !thank you !

自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment

本文档对quartus与modelsim运用操作描述十分详细，对初学者，会有很大帮助！(Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!)

基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART )

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

自适应均衡器

说明：  fPGA中的竞争冒险现象的来源及其解决方法(FPGA in the source of the phenomenon of competitive risk-taking and their solutions)