用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用...

自己根据xapp1052修改的源代码，已经编译成功，并应用在开发板上。(According xapp1052 own modified source code has been successfully compiled and used in the development board.)

这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.

Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol

用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)

4 bit ROM for Quartus

数码管显示程序，可以显示当前的数值，可以动态显示和静态显示 可以选择显示方式-Digital tube display program can display the current value, you can dynamically display and static displays can choose to display

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

说明：  基于FPGA设计的一段测试VGA接口的VHDL小程序\功能为在显示器上间隔显示横条、竖条以及棋盘格等彩条信号，希望对初学FPGA驱动VGA接口的电子爱好者有用(FPGA-based design of a VGA interface VHDL test applet \ functions for the intervals shown in the display bar, vertical bars and checkerboard patterns and other signals of color, hope for beginners FPGA VGA interface driver useful for electronic enthusiasts)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

Verilog-RISC CPU