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dds(1)
基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
- 2017-07-11 16:36:38下载
- 积分:1
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频率计实验程序代码
说明: XC7A35TCSG324-1的Verilog频率计程序,支持十分频,支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)
- 2019-12-24 13:40:45下载
- 积分:1
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Great guide for writing VHDL
Great guide for writing VHDL
- 2023-05-21 15:20:03下载
- 积分:1
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IOLED
基于单片机显示原理的IO和LED显示原理(Based on the principle of IO chip and LED display shows the principle)
- 2011-09-02 17:09:24下载
- 积分:1
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SZ-VHDL
系统数字逻辑电路设计方法以及示例的介绍,分析较好,有价值(System digital logic circuit design methods and introduce examples, analyze good and valuable)
- 2014-03-30 08:34:05下载
- 积分:1
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util_gmii_to_rgmii
说明: rgmii代码编写,实现rgmii接口功能,可进行参考设计(The rgmii code is written to realize the function of rgmii interface, which can be used for reference design)
- 2021-03-18 10:19:20下载
- 积分:1
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canny_edge_detector_latest2
very good code for edge detection based on vhdl programming.
- 2021-04-14 13:08:55下载
- 积分:1
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This is what I did do a UART transmitter when the source and hope for all of us.
这是我做UART时候做的一个发送器的源码,希望对大家有用。-This is what I did do a UART transmitter when the source and hope for all of us.
- 2022-03-25 00:51:09下载
- 积分:1
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adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的
adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的-ADC0809
- 2022-09-16 00:25:02下载
- 积分:1
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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分:1