Electronic code locks, FPGA

本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...

嵌入式应用开发技术白金手册源代码 嵌入式应用开发技术白金手源代码-this is a vhdf code

说明：  Verilog语法教程，适合初学者，详细(Verilog instruction book)

一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article

实现十字路口简单交通灯的verilog hdl源代码,可以实现-Realize a simple traffic lights at the crossroads of the verilog hdl source code, can be achieved

说明：  高速宽带数字调制技术的研究，该论文也是非常经典的，希望对大家有帮助(High-speed broadband digital modulation technology, the paper is also very classic, I hope all of you help)

有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.

高通滤波器的仿真（由matlab和simulink两种方法实现）源文件以及图片示例(Simulation of the high-pass filter (implemented by the two methods matlab and simulink) source files as well as images example)