一个用VHDL完成的8位数显的16进制的频率计

用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)

频率计，vhdl语言， ispDesignEXPERT-Frequency meter, vhdl language, ispDesignEXPERT

VHDL开发程序，有程序仿真的截图，方便验证调试结果。并有程序说明(VHDL 驴 陋 垄 鲁 脤臑貌 拢 卢 脫臑 鲁 脤臑貌 脗脮忙渭脛 陆 脴脥 录拢卢路陆卤 茫脩茅脰 陇 渭 梅 脢脭 陆 谩 鹿 没 隆 拢 虏 垄 脫臑 鲁 脤臑貌脣渭脙 梅)

说明：  以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

很好的quartus软件仿真教程，flash版。-Good quartus software simulation tutorials, flash version.

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

运用matlab实现fft变换，用于地震资料频谱分析！(FFT transform)