一个用VHDL完成的8位数显的16进制的频率计

完整的OFDM仿真程序，包括QPSK,16QAM调制，基于MATLAB，各个步骤都有详细的说明。(OFDM simulation program, based on the complete MATLAB, every step is described in detail.)

说明：  掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

making a simple clock using altera vhdl

开源的ULPI IP核，可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)

4*4按键扫描电路，用数码管显示0~F，基于VHDL语言设计，包括按键扫描，数码管扫描，数码管显示，按键消抖等代码

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

这是基于MIMO-OFDM的对CFO进行估计的源程序，对分析此同步算法有着非常重要的作用。(This is based on the source of the MIMO-OFDM of the CFO estimation, on the analysis of this synchronization algorithm has a very important role.)

该代码实现了IIC对24C02的读写，写采用页写的方式，读采用随机的方式。(This code implements the IIC on 24C02 read and write, write, write using the page mode, read random way.)

通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.

鼎lpc1788尚开发板的vga的显示，1024x768(lpc1788board,lcd to vga display,1024x768)