汽车自动化

这是我自己写的两个8位二进制数的乘法程序，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote two eight binary number multiplication procedure, In xilinx Spartan3E debugging has been successful, with the show to share with you!

设计一个可编程间隔定时器，完成8253的功能，实现以下几点要求： 1、 含有3个独立的16位计数器，能够进行3个16位的独立计数。 2、 每一种计数器具有六种工作模式。 3、 能进行二进制/十进制减法计数。 4、 可作定时器或计数器。 -The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the timer or counter.

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)

Vhdl实用教程，可帮助初学者迅速掌握VHDL的编写-Vhdl practical tutorials to help beginners to grasp quickly the preparation of VHDL

Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.

VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners

能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

Ovo sto saljem je tutorijal 7 sa vhdlom

说明：  ? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

基于APB总线的UART详细设计方案和实现(APB-based detailed design and implementation of UART)