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HDB3modelsim
说明: HDB3编码通过verilog实现,通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分:1
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8251的完整的功能的实现,可以进行编译,综合.
8251的完整的功能的实现,可以进行编译,综合.-8251 complete function of the realization can be compiled and integrated.
- 2022-02-25 05:27:00下载
- 积分:1
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EncoderUsingif
encoder using else if statement
- 2015-05-21 13:41:00下载
- 积分:1
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TechAss-2006
un controller pi par le langage VHDL xilinx ise design 13.2
- 2013-12-16 22:53:24下载
- 积分:1
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the major digital TV front
主要完成数字电视前端信号处理和缓冲作用的verilog源代码,可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
- 2022-04-09 13:15:30下载
- 积分:1
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一种基于LUT的预失真方法。其中的一部分,有参考价值。
一种基于LUT的预失真方法。其中的一部分,有参考价值。-one method of DPD based on LUT
- 2022-06-30 17:35:36下载
- 积分:1
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vhdl code for decoder and detemines the basic mechanism of gates of decoder
vhdl code for decoder and detemines the basic mechanism of gates of decoder
- 2022-01-25 15:11:52下载
- 积分:1
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DE2_UserManual
DE2使用手册,介绍DE2的所有组成元件,使用方法,还有相应的实例。(DE2 User Manual, describes all the components DE2 components, using the method, there is a corresponding instance.)
- 2010-11-14 12:43:48下载
- 积分:1
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Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考....
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.
- 2022-12-08 19:40:03下载
- 积分:1
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初学VHDL有用的,了解后对复杂设计有很大帮助.
初学VHDL有用的,了解后对复杂设计有很大帮助.-VHDL beginner useful understanding of the complexity of the design has been inspired by them.
- 2022-08-10 16:58:07下载
- 积分:1