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VHDL-development
VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)
- 2015-03-11 10:57:53下载
- 积分:1
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Chip_hardware_description_language_related_program
硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)
- 2010-07-28 07:53:40下载
- 积分:1
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Quartus senior io distribution, manual example
quartus 中,高级io分配,手动的例子-Quartus senior io distribution, manual example
- 2022-07-11 02:00:46下载
- 积分:1
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How to Connecting Xilinx FPGAs to the Philips
How to Connecting Xilinx FPGAs to the Philips
- 2022-08-14 17:50:57下载
- 积分:1
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IDT7005
双端口静态RAM的VHDL程序,具体芯片型号为IDT7005(DUAL-PORT
STATIC RAM)
- 2014-04-03 11:40:53下载
- 积分:1
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rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分:1
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IIR
使用verilog语言描述的二阶巴特沃斯IIR滤波器,程序中有参数说明,已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)
- 2013-06-18 16:30:35下载
- 积分:1
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tcd1209d
TCD1209D驱动程序
Verilog语言(TCD1209D driver Verilog language)
- 2021-04-08 09:49:01下载
- 积分:1
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VHDL描述的简易图像缩小模块,将PAL制720×576的图片缩小为512×410,采用最近临域法,13.5MHz时钟下可实时处理PAL视频。...
VHDL描述的简易图像缩小模块,将PAL制720×576的图片缩小为512×410,采用最近临域法,13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
- 2022-06-11 23:09:14下载
- 积分:1
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网卡的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.
网卡的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.-NIC
- 2022-03-01 02:33:22下载
- 积分:1