ac97 VHDL core

说明：  用verilog语言开发俄罗斯方块小游戏(Developing Tetris game with Verilog language)

本文提供了一种CMOS控制器，使Nios-II可以利用CMOS控制器控制CMOS，并允许在CMOS图像上传送SDRAM。在DE2-70平台上运行

实现同一个时钟输入,可以实现多分频,在一个时钟的驱动下-Realize with a clock input, can realize multi-frequency, in a clock-driven

说明：  FPGA实现的AD采样控制程序的源码，欢迎大家下载(FPGA implementation of the AD sampling control)

verilog例子，有130多个，值得参考，新手很有帮助-Verilog example, there are more than 130, it is also useful, very helpful to novice

Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现(Verilog，Sobel Operator)

用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.

To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.

Fpga开发应用，jtag方面的源代码，VHDL-Fpga development and application, jtag in the source code, VHDL

FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)