Spartan 3E

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

uart发射机Verilog HDL代码(Verilog HDL code uart transmitter)

基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2

说明：  AES TSAPI Retrieve Event in Non-blocking Mode

说明：  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)

数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能(Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function)

10对于进入密码锁的按键，假设复位后七个灯显示0，使用sw1、sw2两个键输入，只要按sw1键，并使七个灯显示每秒速度加1的值，但释放sw1键后停止。

system gen & accel dsp 培训资料-system gen & accel dsp

此论文想详细阐明了用FPGA做硬件处理，集成SOPC功能实现MVB通讯协议的解决方案，可以运行在alter fpga上面。(This paper expounds in detail the processing to do with FPGA hardware, integrated solutions for SOPC function of the realization of MVB communication protocol, can run in alter FPGA above.)

用vhdl写的-using VHDL write