Spartan 3E

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)

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说明：  i2c module，有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)

de2 70 开发板的演示程序，verilog语言编写，视频输入输出(de2 70 development board demo program, verilog language written, video input and output)

说明：  FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)

可实现找钱功能的自动售邮票机，可买两种邮票，一元的和五角的-Money function can be realized stamp vending machine, to buy two stamps, one dollar and the Pentagon

3g-sdi驱动器，用于全高清视频FPGA解决方案(3g-sdi driver)

imp book for cmos technology