用于FPGA的反量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

使用vhdl语言实现了数字滤波器，在Spartan-6上验证通过，最大支持240阶。源代码中滤波器为低通滤波器，可通过matlab中的fdatool工具生成滤波器系数，然后更改滤波器的通带和阻带。

FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机(FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game)

说明：  1、能正确显示输入信号频率； 2、测量频率范围为1Hz ~ 999999Hz； 3、测量结果以十进制数字显示； 4、能测量幅值较小的信号频率； 5、有自动刷新输出数据的功能（如5s刷新一次）； 6、有自检模块（如产生100Hz的校准方波）；(1. It can correctly display the input signal frequency; 2. The frequency range of measurement is 1Hz ~ 99999hz; 3. The measurement results are displayed in decimal; 4. It can measure signal frequency with small amplitude; 5. It has the function of automatically refreshing the output data (e.g. once in 5S); 6. Self checking module (such as generating 100Hz calibration square wave);)

基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....

如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.

一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文(master and doctor dissertation)