VHDL 加法器

modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)

基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)

8051核的vhdl原代码。-8051 core VHDL source code.

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!

請設計一個8位元移位暫存器，規格如下： 當控制線S1，S2輸入為00時，平行載入； 當控制線S1，S2輸入為01時，在一時脈內向右shift 1位元； 當控制線S1，S2輸入為10時，在一時脈內向右shift 2位元； 當控制線S1，S2輸入為11時，在一時脈內向右shift 3位元 (Serial Adder)

实现与电脑端串行数据发送与接收，波特率为9600(Realize serial data sending and receiving with the computer terminal)

数字设计和计算机体系结构：用verilog语言描述3-8译码器的设计与实现(Digital design and computer architecture: use verilog language describe 3-8 decoder design and implementation)

设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report

4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写(4-bit adder booth algorithm, the learning of computer organization help, verilog language)

用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder