VHDL 加法器

基于EPM1270的EProm at24c02 驱动-Based on the EPM1270

用Verilog实现的呼吸灯，用Verilog实现的呼吸灯(Verilog huxideng)

说明：  该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)

实现SIGMA-DELTA Modulator的veriolog代码(sigma-delta moudulator for RFPLL )

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger

说明：  MATLAB to HDL Code conversion

sdram controller vhdl

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)

verilog 编写的比较最大值最小值得的程序，而且能够求出最大最小值在ram中存储的位置，测试通过下载即用(Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values ​ ​ can be obtained is stored in ram position, the test that is used by downloading)