I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能

8051核的vhdl原代码。-8051 core VHDL source code.

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

interruption routine for PIC16F877

VHDL开发环境，四人抢答器，实现了四个人能同时抢答的功能。-VHDL development environment Answer four, and the realization of the four functions at the same time Answer.

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)

开源的ULPI IP核，可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)

VHDL Design of BCD to 7-segment decoder using PROM

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.

说明：  Verilog 入门,如果你要很了解Verilog你不用先谖完一本厚厚的书还弄不清楚Verilog到底在干啥事,这份资料有助於快速了斛Verilog(Verilog Basic, If you try very hard to understand verilog by read a thick book, try read this first you will get a quick understanding of verlog.)