I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

说明：  uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)

decoder 2-4 digital core

基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode

采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件-AD using high-speed storage oscilloscope design, based on EP1C3 board GWADDA board storage oscilloscope, which has the documentation

LED闪烁的VHDL代码

沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)

基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序，用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation

根据按键控制状态机状态转换，内含仿真波形文件