I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

主要用来介绍如何编写高质量的verilog程序的(Is mainly used to describes how to write high-quality verilog programs)

8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

一种基于FPGA的通用微处理器设计-A general-purpose FPGA-based microprocessor designs ....

基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.