I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能

[数字通信同步技术的MATLAB与FPGA实现——AlteraVerilog版]书中资源代码，非常好，分享， 希望大家下下！( U651 u0B3 u09108 u09108 u0103 u0101 u7801 uFF0C u975E u5HR U597D uFF0C u5206 u4EAB uFF0C u5E0C u671B u5927 u5BB6 u4E0B u4E0B uFF01)

一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using

扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation

msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures

该源码表述了ecc算法如何用vhdl实现RSA（Ron Rivest，Adi Shamir，Len Adleman三位天才的名字）一样，ECC（Elliptic Curves Cryptography，椭圆曲线密码编码学）也属于公开密钥算

SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore

IIC主设备的代码实现（verilog),从设备模型-IIC main equipment of the code (verilog), from the device model

Quartus_II_9.0破解器有明确的破解Quartus_II_9.0的步骤(Quartus_II_9. 0 cracked the clear cracked Quartus_II_9. 0 steps)

本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book

reversible Data Hiding in Encrypted Images by Reserving Room Before Encryption