I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能

FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议

Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.

对于32位寄存器前导零个数的计数，一个简单的程序(32 registers a leading zero number of counts, a simple procedure)

Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo"s---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

FPGA实现基于cordic算法的指数函数的程序(FPGA implementation of an exponential function program based on the cordic algorithm)

说明：  artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)

蒙特卡洛仿真图 这个程序对2psk信号进行仿真 前提是把信号能量归一化了 (This programme intend to realize the simulation of 2DPSK through MonteCarlo experiment. intends )