基于vhdl的PWM发生器

这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)

VHDL控制VGA 在显示器上显示图形，分辨率800X600，晶振50Mhz-VGA control with VHDL

altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.

inter integrated circuit i2c protocol

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

用VHDL语言实现一Mealy型时序电路，并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)

说明：  通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

CH4CH2CH1VHDL 数字电路参考书所有程序7-CH4CH2CH1VHDL digital circuit reference all proceedings 7

FPGA源代码公布，包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序，LED静态显示ADC0809 VHDL控制程序，DAC0832 接口电路程序

vc707 board ucf xdc files