This is a debugging software online CPLD. Be able to meet the general requiremen...

自动售货机VHDL程序与仿真的vhdl的源代码-Vending machine VHDL procedures and simulation of vhdl source code

串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)

说明：  EGO_1流水灯显示代码步骤过程全都有适合初学者练手(EGO_1 nxoiaocijpwjcpoewopvkpowevko)

A VANET research program

可测试74LS00，74LS01，74LS02，74LS03等等芯片的功能是否正常。

自编的64B/66B编码程序，下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

vhdl project at sbu uni in iran uart

矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境(implement of inverse matrix)

异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control