This is a debugging software online CPLD. Be able to meet the general requiremen...

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

一个基于fpga的源程序，对于初始接住的人来说很有帮助-FPGA-based source for the initial very helpful for those who catch

说明：  SHA-1加密算法的IP核，内涵文档，仿真测试文件(SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file)

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)

least mean square algo implemented on verilog

FPGA程序,使用Verilog语言生成1个脉冲可调的PPS脉冲信号。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

UC1608 24064驱动 COG LCD驱动程序(UC1608 24064)

控制8个发光二极管中的一个发光二极管发光，其它7个发光二极管都出于截止状态，发光二极管的导通顺序按照向左或向右两个方向移动，并且通过按键控制发光二极管循环发光移动的方向。(Control of a light-emitting diode light-emitting eight light-emitting diodes, the other seven light-emitting diodes for the cut-off state, light-emitting diode conduction order in accordance with the left or right move in both directions, and light-emitting diode cycle luminous button control mobile direction.)