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fifo
说明: FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)
- 2020-12-03 16:59:25下载
- 积分:1
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高速双端口RAM的vhdl实现。包含仿真波形
高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
- 2023-08-22 14:25:04下载
- 积分:1
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uart
UART串口的verilog源代码,完全正确...........(UART serial Verilog source code, completely correct ...........)
- 2009-03-02 14:44:16下载
- 积分:1
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Chapter11-13
第十一章到第十三章的代码
本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示。(Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.)
- 2009-11-17 13:57:09下载
- 积分:1
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rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分:1
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Image-Interpolation-Algorithm
文档包括双线性插值算法和最近邻域算法的详细介绍,以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)
- 2020-06-30 21:40:01下载
- 积分:1
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完成的是RS422信号的计数功能,并产生一定的触发信号
完成的是RS422信号的计数功能,并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals
- 2022-04-14 14:08:50下载
- 积分:1
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S04_基于ZYNQ的HLS 图像算法设计基础
说明: VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
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一个多路复用器的例子,用VHDL语言写的。
A Mux example written in VHDL.
- 2023-01-13 15:05:04下载
- 积分:1
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syn_rd_wr_fifo
该代码实现了FPGA对USB芯片68013的读写,语言是VERLOD,试验通过。(The code to achieve the FPGA read and write 68013 on the USB chip, the language is VERLOD, through the test.
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- 2015-05-02 14:34:16下载
- 积分:1