VHDL描述的时钟分频电路，用途广

一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source

qspi接口控制，指令包括spi、dual spi、quad spi，通过验证，供参考(Qspi interface control, including spi, dual spi, quad spi, for reference.)

quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE

c54x的VeriLog程序代码 也是opencoreip-C54x is the Verilog code opencoreip

8位并行转穿行发送程序，波特率可自行设置，经检验有实用效果(8-bit parallel transfer walk through the sending program, the baud rate can be set up their own practical effect inspection)

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)

the basic system of nexys3(soft core)

wishbone接口的设计，在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)

verilog 模糊PID 通过修改MIF文件 可以完成单个参数整定(FUZZY pid by verilog HDL)