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bpsk-qpsk
this is bpsk code in matlab
- 2011-10-20 02:49:32下载
- 积分:1
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DDS
基于ARM的DDS信号发生器设计,可以产生各种信号的波形,生成所需要的信号,可供实验用(DDS signal generator based on ARM, can produce a variety of signal waveform can be used for experiment)
- 2013-03-29 18:49:52下载
- 积分:1
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beep_interface
这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)
- 2013-05-05 21:07:18下载
- 积分:1
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wallace multiplier trees for 4:2
- 2022-02-10 01:12:10下载
- 积分:1
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i2s串行线广泛用于音频通信中,这里包括了master和slave的代码.
i2s串行线广泛用于音频通信中,这里包括了master和slave的代码.-i2s serial lines widely used in audio communication, here including the master and slave codes.
- 2022-04-15 12:56:02下载
- 积分:1
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Altera company s FPGA using VHDL to the development, use quartus2 9.0 software E...
使用altera公司的FPGA进行VHDL开发,使用quartus2 9.0 软件在EP1C3T144C8开发板上实现跑马灯输出。-Altera company s FPGA using VHDL to the development, use quartus2 9.0 software EP1C3T144C8 Development Board to achieve ticker output.
- 2022-02-02 20:51:33下载
- 积分:1
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RS-code
说明: 我测试过的!Verilog HDL实现RS编码。(I' ve tested it! RS coding Verilog HDL implementation.)
- 2010-04-12 20:30:36下载
- 积分:1
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CCDDRIVE(TCD1206UD)
关于一款线阵CCD TCD1206UD 的驱动设计,波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)
- 2020-11-14 09:19:42下载
- 积分:1
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用verilog实现了一个数字秒表的设计
用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
- 2022-08-03 10:15:12下载
- 积分:1
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1
说明: 一个解决除法溢出的例子,可以学习到很多,注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
- 2013-12-24 09:19:13下载
- 积分:1