有关FPGA芯片的管脚的封装的一些资料。

实现了三种乘法器，可以进行性能比较，比较有较之-multi

说明：  ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。(ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.)

fpga paper function fff(fpga paper function)

UART串口的verilog源代码，完全正确...........(UART serial Verilog source code, completely correct ...........)

SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

design through verilog hdl

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

说明：  CC217编程序，verilog实现，串行输入串行输出(CC 217 program, to achieve Verilog, serial input serial output)

说明：  希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)