基于SOPC EP2C5开发板的I2C总线的A/D D/A例程

an 16 bit ripple carry adder

千兆以太网设计，包括组包解包，可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)

此为实现第14.7.9章所需的激励文件 该代码为门级RTL描述。(Stimulus file to verify Section 14.7.9 the functionality of gate vs. RTL description.)

4个7段lcd同时显示的程序，已经在digilent的nexy2板上通过验证，非常好用易懂，适合初学者学习-display 4 leds

基于ALTERA AVALON BUS 的 VGA Controller 设计(ALTERA AVALON BUS VGA Controller )

vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change

有用的VHDL源代码-useful VHDL source code

LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language

Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C

这是用verilogHDL写的m序列发生器，简单易用，代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)