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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分:1
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FPGA UART的发送等
FPGA UART transmit and so on
- 2022-01-24 13:54:39下载
- 积分:1
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vhdl经典源代码――LCD控制,入门者必须掌握
vhdl经典源代码――LCD控制,入门者必须掌握-vhdl classical source code-- LCD control, beginners must master
- 2022-03-20 08:17:37下载
- 积分:1
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基于DE2开发板的VGA显示模块,仅供大家参考
基于DE2开发板的VGA显示模块,仅供大家参考-DE2 development board based on the VGA display module, for your reference
- 2022-03-21 02:14:24下载
- 积分:1
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Code
用于数字积分器的设计,主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)
- 2011-11-23 21:31:03下载
- 积分:1
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calibration
CS5460校准程序,控制器为C8051F310,SPI通信协议,可以作为电表芯片示例(CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample)
- 2011-08-05 00:42:09下载
- 积分:1
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fir-filter
11阶fir数字滤波器的verilog程序设计,线性相位,系数量化处理(11 order of fir digital filter verilog programming, linear phase, the coefficient quantization)
- 2012-03-05 10:33:03下载
- 积分:1
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xp2syscloclkpll
这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多(Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar)
- 2007-10-31 21:03:07下载
- 积分:1
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TR0114 VHDL Language Reference
TR0114 VHDL Language Reference
- 2022-03-22 11:52:47下载
- 积分:1
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adder_array
adder_array的设计。加法器阵列设计,顶层模块,四步流水,21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)
- 2013-04-17 00:19:05下载
- 积分:1