FPGA驱动VGA接口显示字符

说明：  将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

说明：  LIUSHUIDENG VHDLYUYAN XIADE SHUIDENG(LEDWATER I WRITER IT MYSILF.IT'S EASY ! YOU CAN WRITER IT,TOO)

异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )

acousting fingerprint enhancement

内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.(This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.)

8 bit cpu vhdl design code not tested

vhdl code for obtaining video output through vga port

基于分裂基的蝶型FFT，用C实现，经过测试，没有错误，可以直接拿去使用。(Based on the division of FFT butterfly type, use C implementation, tested, no error, can directly use. )