It is a fir to implement in a FPGA. It s not desenvolved for me it is a good wor...

说明：  用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)

modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!

基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!

基于vhdl的dds任意函数发生器的实现和仿真

I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.

picoblaze实现串口通信...难道一定要20个字吗?-implement uart communication base on picoblaze

不足20元的PCI设计，含ABEL源代码。-PCI design less than 20Yuan ,including ABEL code

为了便于计算结果在FPGA中后续的计算和ip核中的调用，本代码输入信号为普通浮点型数据，输出为32位表示的浮点型数据。

说明：  环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)