不足20元的PCI设计，含ABEL源代码。

摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)

verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )

流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!

SDIO slave verilog code

Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)

fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University

用vhdl编写的简易电子中设计，经过测试成功，且用记事本上载，无需阅读器进行阅读。-Use of VHDL in the preparation of simple electronic design, has been tested successfully, and use Notepad to upload without reader reading.

简易双口ram，使用两个ram ip core，一个写的同时另一个读，并且包含按键使能和数码管以及流水灯显示(Simple dual-port ram, two ram the ip core, a write while another read, and contains buttons to enable digital pipe and the water light show)

多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card

实现basys3板子的串口通信，内容非常纤细，还带有数码管显示(Realization of serial communication of basys3 board)