不足20元的PCI设计，含ABEL源代码。

说明：  可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)

七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)

一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)

ZardWars Files ------------------------------

应用VHDL语言编写交通灯的控制程序。 熟悉该语言的基本用法。-Application of VHDL language of the control procedures of traffic lights. Familiar with the basic use of the language.

xlinx fpga实现fft功能，利用ip核，包含源程序及完整工程文件，直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)

常用的VHDL语言编写的LED灯控制程序,这是教学用的，开发板采用的是EPM240T100C5N，买开发板时附带的程序

说明：  一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)

EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals. )

这是利用VHDL编写的一个CRC32的代码，文档只有代码，具体原理请参考其他文献-This is the use of VHDL prepared a CRC32-code, the document is only a code Please refer to specific tenets of other literature