基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！...

此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)

多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )

说明：  在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)

Anticipated Adder for Xilinx

It is a example about LCD by VHDL code

filter kalman mppt for PV

原创：cos函数和sin函数的VHDL实现，很实用(cos of the VHDL implementation)

verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)

VHDL语言设计；功能描述：键盘扫描，不包含去抖电路-VHDL language design Function description: the keyboard scanning, does not contain a circuit debounced

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures