-
01_基于ZYNQ的FPGA基础入门
说明: VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)
- 2020-06-17 12:00:01下载
- 积分:1
-
m_ca7
verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
- 2011-10-26 14:33:59下载
- 积分:1
-
fifo
FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)
- 2020-12-03 16:59:25下载
- 积分:1
-
Vending machine design, source code, in the hope that useful
自动售卖机的设计,有源代码,希望对大家有用-Vending machine design, source code, in the hope that useful
- 2022-01-22 14:24:49下载
- 积分:1
-
VGA图象显示控制器设计,实现在VGA显示器上显示图象.
VGA图象显示控制器设计,实现在VGA显示器上显示图象.-VGA image display controller designed to achieve the VGA display shows images.
- 2022-03-21 07:20:30下载
- 积分:1
-
ADC VHDL 代码
使用VHDI Dispaly字符。显示了一个模拟的正常工作的LCD控制器硬件实现。这种模拟演示了不同的状态机协同工作的方式。作为初始化序列完成时,主状态机的命令的状态开始。
- 2022-02-24 19:19:54下载
- 积分:1
-
给予MSP430F147的串口通讯程序,能帮助你了解MSP430系列单片机和串口通讯的基本方法...
给予MSP430F147的串口通讯程序,能帮助你了解MSP430系列单片机和串口通讯的基本方法-give MSP430F147 Serial communication process can help you understand the MSP430 MCU serial communications and the basic methods
- 2022-03-30 13:28:48下载
- 积分:1
-
clock_seg
用FPGA分频,做一个有时分秒的时钟,并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)
- 2013-05-20 13:53:06下载
- 积分:1
-
BCD_to_7_seg_decoder
BCD to 7 segments display decoder
- 2015-06-15 22:36:01下载
- 积分:1
-
Altera_Audio
针对Altera的DE2/ DE1交互板的音频核心的音频编解码器(编码器/解码器),并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1
Boards and provides an interface for audio input and output.)
- 2015-04-01 22:21:49下载
- 积分:1