高级加密标准AES的FPGA实现，支持128，256密钥长度格式

signaltap 中文说明，内容详细。 ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)

硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.

可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； (Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The phase adjustable sine wave, square wave duty ratio is adjustable )

浙江大学体系结构实验代码 实现流水线的forwarding(Architecture, Zhejiang University Experimental code pipeline forwarding)

用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

六个数码码动态扫描接口程序，用VERILOG语言编写的-Six digital code dynamic scan interface program, using Verilog language

this come from alter ,you can look and find it on line about h263.

sender的verilog 利用fpga实现-sender using the Verilog FPGA realize

四选一选择器,输入四个,输出1个.当NM=00时选A 当NM=01时选B 当NM=10时选C 当NM=11时选D-four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D