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用VHDL实现十六位移位乘法器 才有移位相加法来实现
用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
- 2022-04-17 17:23:11下载
- 积分:1
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软件开发环境:ISE 7.1i
仿真环境:ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共...
软件开发环境:ISE 7.1i
仿真环境:ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器;
2. 工程在project文件夹中,双击traffic.ise文件打开工程;
3. 源文件在rtl文件夹中,traffic.v为设计文件,traffic_tb.tbw是仿真波形文件;
4. 打开工程后,在工程浏览器中选择traffic_tb.tbw,在Process View中双击“Simulation Behavioral Model”选项,进行行为仿真,即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit
- 2022-08-09 15:58:02下载
- 积分:1
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13.2_MotionDetec
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)
- 2020-10-23 20:57:22下载
- 积分:1
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Commonly used phase
常用的锁相环技术,此程序是我在设计高频电路中运用的,具体见程序,经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging
- 2022-10-15 08:30:03下载
- 积分:1
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CircuitDesignwithVHDL[1]
这主要是学习vhdl和fpga设计的一些资料(study for vhdl and fpga)
- 2009-05-13 09:31:26下载
- 积分:1
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Tutorijal 6
Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分:1
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quartus2tutorial
说明: 自己收集的quartus2 教程以及vhdl语言教程,和如何在quartus中使用modism仿真 ,希望对大家有用(Tutorial quartus2 own collection, as well as language tutorials vhdl and quartus how to use modism, useful for all of us hope)
- 2009-07-27 09:09:22下载
- 积分:1
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ALTERA Cyclone1C20 Nios开发板,protel99格式
ALTERA Cyclone1C20 Nios开发板,protel99格式-ALTERA Cyclone1C20 Nios,protel99
- 2022-01-23 10:08:20下载
- 积分:1
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FIFO_Buffer(verilog)
这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)
- 2021-04-22 13:38:49下载
- 积分:1
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1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES...
1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-04-30 11:01:06下载
- 积分:1