sender的verilog 利用fpga实现

Pipeline processor verilog components

黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)

说明：  图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

MMC卡的VHDL源代码实现，经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test

用verilog语言编写的串口读写程序，波特率可调，亲测可用。(this is a program for UART by verilog, which is useful.)

用VERILOG语言实现的通用异步串行收发器（RS232收发器），波特率可设置，通讯稳定，已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)

its the vhdl stuff for ddr sdram controller nice one easily understandable

Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.

开发工具是quartus II 7.0以上版本，这是一个verilog语言的分频器设计，个人作业设计，供参考学习(verilog，quartus II 7.0)

这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)