sender的verilog 利用fpga实现

说明：  实现数字频率合成实验，加载数据ram,形成波形(The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform)

四线电阻式触摸屏，ads7846控制显示触摸坐标(Four-wire Resistive Touch Panel, ads7846 touch control display coordinates)

《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3

说明：  URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

说明：  access must be conf urr arr

RS(255,223)编码器程序 从一本书上看到的，很不错的(RS(255,223) encode , very good good good )

上海交通大学电子信息与电气工程学院VHDL经典教程-Shanghai Jiaotong University Electronic Information and Electrical Engineering, Institute of Classical VHDL Tutorial

vhdl code for cyclic cfft control

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.

该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)