这是改变，你可以找到它在网上视频。

This code for countor . it is design in verilog HDL.

最终FFT 64点使用定点。

一个以太网卡的硬件描述，可以参考进行设计网卡芯片。-an Ethernet card hardware description, reference card chip design.

说明：  基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!

Simulation and Synthesis Techniques for Asynchronous FIFO Design

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

This code that genetes a square, sawtooth and a triangular waveform. It is useful for designing a function generator in VHDL.

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

基于单片机显示原理的IO和LED显示原理(Based on the principle of IO chip and LED display shows the principle)