VHDL语言进行，调试通

this file is vhdl code of alu

带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!

一个具有“百分秒，秒，分”计时功能的数字跑表，可以实现一个小时以内的精确至百分之一秒的计时。 数字跑表的显示读者可以通过编写数码管显示程序来实现，本训练只给出数字跑表的实现过程。 读者还可以通过增加小时的计时功能，实现完整的跑表功能。-A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.

DS18B20温度测量程序 之后用于在LCD显示屏上显示对应的温度(DS18B20 test code)

rc6 algorithm designed based on verilog and is verified

Mano s cpu for Man s instructions

ahb to apb master verification

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

maxplus2为开发环境 vhdl编写的自由 计数器 程序-maxplus2 VHDL environment for the development of free counter preparation procedures

verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)