VHDL语言进行，调试通

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)

SPI协议的VHDL/Verilog语言实现。(SPI agreement VHDL/Verilog language.)

在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving

简易环形FIFO的设计、简单异步串行通信接口设计等-verilog

这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!

PS2 Module for Altera DE2

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

rc6 algorithm designed based on verilog and is verified

这个课程设计的题目是模拟电压采集电路路与程序设计,报告书的内容都比较详细. (The topics of this course design is an analog voltage acquisition circuit Road and program design, the contents of the report are more detailed.)