modelsim的一个非常好的教程，有程序源码，PPT，word教程

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

this a vhdl code for usb-this is a vhdl code for usb

友晶 altera DE2开发板中文用户手册，对DE2开发板的完整介绍。(DE2 development board Chinese user manual, a complete description of the DE2 board.)

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!

文章运用分级抽取和多相滤波的方法改进传统CIC滤波器的结构,降低了系统工作频率,运用幅度改进函数(ACF)和外加级联余弦预滤波器的技术改进了滤波器频率响应,提出了一种高效的算法结构,改善了通带损耗,增大了阻带衰减,对CIC滤波器的实际应用和深入研究有着现实意义。 (Article the use of hierarchical multi-phase extraction and filtering methods to improve the structure of the traditional CIC filter, reducing the system operating frequency, the use of margin to improve the function (ACF) and the cosine cascade plus pre-filter technology to improve the filter frequency response, the an efficient algorithm to improve the pass-band loss, increases the stopband attenuation of the CIC filter in practical applications and in-depth study has practical significance.)

xilinx spartan6的pcie pio源代码(xilinx spartan6 pcie pio demo)

fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program

VHDL数字频率计（1）频率测量范围： 10 ～ 9999Hz 。 （2）输入电压幅度 >300mV 。 （3）输入信号波形：任意周期信号。 （4）显示位数： 4 位。 （5）电源： 220V 、 50Hz -vhdl