modelsim的一个非常好的教程，有程序源码，PPT，word教程

VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2

Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)

基于FPGA的误码测试仪 （已注释） --锁相环-M序列生成模块--数据接口模块- --模拟信道模块---本地M序列生成模块--同步模块--误码统计模块--显示模块-(FPGA-based BER tester)

其中包括AD9226的原理图和应用程序，可以参考完成其他编程(Including AD9226 schematics and applications, you can refer to complete other programming)

说明：  用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)

this project is about FIR FIlter By VHdl codes in the ISE.

基于FPGA的1553B总线编码解码器的设计-1553B Bus FPGA-based codec design

基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah

用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure