Based on quartus a 3

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)

ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助(ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners)

DDR3 控制器，axi4_full 模式， burst长度为16，应用于xilinx平台。(DDR3 interface controller， axi4_full working mode with burst length 16, can operate on the xilinx platform.)

用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted

实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)

本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。(This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and then read the image data processed by the edge filter VGA output to the screen.)

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

说明：  处理器系统，处理器加上存储器，从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)

PS2键盘实验Verilog HDL代码(PS2 keyboard experiment Verilog HDL code)

实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)