Based on quartus a 3

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program

使用FPGA控制AD9288，方便移植，可以拿来直接使用，适合新手学习(Use FPGA control AD9288, easy migration, can be used to directly use for novices to learn)

DDS VHDL include everything of dds AD9914

循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)

应用背景****************************************************************************关键技术这个项目的目的是研究开发板的最大。该项目是实现闪烁的发光二极管具有不同的频率和/关闭时，你按按钮。

FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)

基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)