Based on quartus a 3

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！

交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss

quartus2的中文文档，不是很全，仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)

实现音频的I2S通信，音频柱的显示，及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)

关于FPGA的书籍，介绍了大量的Verilog实例，对初学者很有帮助-Books on the FPGA, introduced a large number of Verilog examples very helpful for beginners

说明：  图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)

verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦(verilog things properly used it, it is an essential learners verilog things oh)

Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear