-
基于VHDL+FPGA的DDS信号发生设计,已经通过调式
基于VHDL+FPGA的DDS信号发生设计,已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
- 2022-06-28 11:38:23下载
- 积分:1
-
CPU-master
说明: misp,五级流水源码,实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)
- 2020-06-16 00:00:07下载
- 积分:1
-
lowpass
低通滤波器(由matlab和simulink两种方法实现)源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)
- 2013-03-13 18:36:40下载
- 积分:1
-
VHDL
控制电话信令
完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)
- 2010-10-22 20:11:38下载
- 积分:1
-
100_Power_Tips_for_FPGA_Designersi
fpga高手设计实战真经100则,最新的FPGA英文书籍,值得参考学习(100 Power Tips for FPGA Designers,The new FPGA English books, worth learning)
- 2013-12-06 19:40:43下载
- 积分:1
-
使用FPGA的FIFO,状态机,乒乓操作等实现了异步UART。
使用FPGA的FIFO,状态机,乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
- 2022-12-07 20:00:03下载
- 积分:1
-
5.7
设计一个简单的FIR滤波器,并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)
- 2015-04-17 18:26:49下载
- 积分:1
-
Flicker_LED
It s Flicker_LED code.Verilog for MaxV.
- 2013-08-08 10:16:32下载
- 积分:1
-
verilog设计点滴经验,对fpga设计人员很有好处
verilog设计点滴经验,对fpga设计人员很有好处-Experience in verilog design
- 2022-11-04 10:05:03下载
- 积分:1
-
signal
能产生正弦波、三角波、方波和e指数衰减的扫频波,且相关参数可调(Can produce sine wave, triangle wave, square wave, and e exponential decay wave sweep and adjustable parameters)
- 2014-05-13 15:15:12下载
- 积分:1