Based on quartus a 3

fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 (fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)

完成十余卷积过程，简单方便，能够这样那样这样，sorry-Convolution process more than a decade to complete, simple and convenient, this can be done this way, sorry

花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!

verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)

利用VHDL语言编写的一个crc功能模块，可下载到FPGA实现功能-use VHDL to prepare a crc function of the module, which can be downloaded to the FPGA functions

全数字锁相环的verilog源代码-全数字锁相环的verilog源代码

延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module

基于FPGA的VGA控制器，可在屏幕显示彩色条纹(A vga controller based on FPGA)

VHDL Code For Full Adder By Data Flow Modelling

这是一个简单的定时器模块使用计数器