Based on quartus a 3

lehmer random number generator method to generate test patterns of circuit

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

是基于FPGA的5620的数模转换芯片底层的应用程序，希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

格子玻尔兹曼方法模拟poiseuille流，半反弹边界，适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code

Clock Divider, divfactor of 18

VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application