-
8_1
一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为:异步清零输入端口rst,输入时钟clk,置数判断输入端口load,移位类型判断输入端口m,数据输入端口data[7:0],输出端口q[7:0]。序列检测器电路端口为:异步清零输入端口rst,输入时钟clk,串行数据输入端口d,输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
- 2020-12-17 08:29:12下载
- 积分:1
-
CPU
C++获取CPU占用率,一个类和一个头文件(Gets the CPU Use rate)
- 2015-01-23 11:15:32下载
- 积分:1
-
verilog-digital-system-design-
verilog数字系统设计,一本很好的verilog学习的书籍,很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)
- 2021-01-10 20:28:50下载
- 积分:1
-
dowload from : www.fpga.com.cn
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn
- 2022-04-23 20:22:54下载
- 积分:1
-
"Verilog HDL Design Guide" 4
《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4
- 2023-06-21 01:20:03下载
- 积分:1
-
用于视频图像编码的8×8DCT变换,可用于MPEG4.H263等VHDL编程
用于视频图像编码的8×8DCT变换,可用于MPEG4.H263等VHDL编程-For video images encoded 8 × 8DCT transform, can be used to MPEG4.H263 such as VHDL Programming
- 2022-03-17 09:22:10下载
- 积分:1
-
异步串行接口电路及数据传输模块设计
设计要求1) 每帧数据供 10 位,其中 1位启动, 8位数据, 1位 停止。2) 波特率为: 9600 。3) 收发误码率
- 2023-09-07 19:10:03下载
- 积分:1
-
数字密码引爆器的输入描述:1、 在开始输入密码以前的等待状态,首先要按READY键,表示目前准备就绪,可以输入数字密码;2、 当引爆事件发生后,应该回到等待状态...
数字密码引爆器的输入描述:1、 在开始输入密码以前的等待状态,首先要按READY键,表示目前准备就绪,可以输入数字密码;2、 当引爆事件发生后,应该回到等待状态,设置WAIT_T键;3、 如果输入密码不正确,此时要操作READY和WAIT_T是不起作用的,必须由设计人员重新设置到等待状态,设置SETUP键,SETUP为内部按键,操作人员应该不能接触;4、 确定密码输入后,要设计一个点火按键FIRE;-digit passwords detonated"s input Description : one at the start and enter the password before the wait state, according to First READY button, now ready to be imported into digital code; Two, when detonated after the incident, should wait for the state to set up WAIT_T bond; three, if a password is not correct, this time to operate READY WAIT_T and is non-functional, the design must be re-installed to wait for the state, set up SETUP button SETUP internal keys, the operator should not contact; 4 to determine the password, to design a FIRE- ignition keys;
- 2022-02-26 18:42:40下载
- 积分:1
-
this come from alter ,you can look and find it on line.
this come from alter ,you can look and find it on line.
- 2022-12-12 10:20:03下载
- 积分:1
-
SOPC_PCI
基于FPGA的pci总线接口设计。。。。。。。。。。。。。(FPGA-based PCI bus interface design)
- 2012-03-28 13:55:33下载
- 积分:1