verilog实现的8051 8051核心，FPGA的有用词汇

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.

实现简单自动售货机的基本功能。投币找零功能，并用Led数码管显示，输出结果用Led显示。(Basic functions simple vending machines. Coin change for function and use Led digital tube display, the output display Led.)

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

VGA interface using Spartan3E board from DIGILENT.Labview .vi

altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience

VHDL实例这是我下载到的最好的VHDL实例，看完这些实例，可以使你有一个长足的进展-VHDL example

design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)

CODE_VHDL_COUNTING 电路时钟运动显示期间 LED 7 （MẠCH ĐẾM ĐỒNG HỒ THỂ 邵族 HIỂN THỊ 领导 7 ĐOẠN）