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uart
用veriolg 语言编写的串口通讯程序,通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )
- 2010-08-16 10:41:03下载
- 积分:1
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模块散播聚集 DMA
模块化分散聚集 DMA 是连续或非连续的转移。如正常 DMA 或散点图聚集 DMA 配置的输入或输出的部分。
- 2022-07-27 03:02:44下载
- 积分:1
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乐曲播放器
用vhdl语言编写的程序,可以播放乐曲,有分频模块,可播放梁祝等歌曲。
- 2022-01-21 18:49:47下载
- 积分:1
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coe
自动计算fir滤波器系数的工具,不妨一试(Automatic calculation of filter coefficients fir tools, try)
- 2009-04-11 17:20:49下载
- 积分:1
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用VHDL语言编程完成数码管0
用VHDL语言编程完成数码管0-255数字的显示-VHDL language programming with the 0-255 number to complete the display of the digital control
- 2023-04-25 03:25:03下载
- 积分:1
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fifo
FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)
- 2020-12-03 16:59:25下载
- 积分:1
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用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制
用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
- 2022-03-12 08:35:58下载
- 积分:1
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relay_test
Simple relay trigger
- 2015-01-28 12:16:35下载
- 积分:1
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EDA
Quatus下用Verilog语言编写的双向交通灯控制系统,内含程序及波形图,注释详细,课程设计(Verilog language Quatus two-way traffic light control system, containing program and waveforms, detailed annotations, curriculum design)
- 2021-01-09 12:58:51下载
- 积分:1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分:1