Traffic Light controller

huffman transform in vhdl language

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)

实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，(vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl )

实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 (Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)

说明：  使用VHDL语言写的AVR单片机IP核， 可以直接使用，已经经过验证， 十分珍贵哦(Written in VHDL language using the AVR microcontroller IP core, can be used directly, has proven very valuable oh)

基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)

74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.