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北斗定位系统卫星下行信号的基带处理部BDSSS-Transmie
北斗定位系统卫星下行信号的基带处理部分——基于FPGA的的直接序列扩频发射机的设计与仿真。,已通过测试。
(Beidou positioning system satellite downlink signal baseband part- based on the design and simulation of the FPGA direct sequence spread spectrum transmitter. , Has been tested.)
- 2012-10-04 00:05:36下载
- 积分:1
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Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can...
用于FPGA的量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-10 06:00:42下载
- 积分:1
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con1
4 bit convoltion with vhdl.
- 2011-10-18 18:18:09下载
- 积分:1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分:1
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I2C-code
I2C总线协议 Verilog源代码.试过,没有错误!可以直接使用(I2C bus protocol Verilog source code. Tried, no errors! Can be used directly)
- 2013-06-03 10:54:17下载
- 积分:1
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用32位NiosII处理器实现RS232通信,可以给初学者一个借鉴。
用32位NiosII处理器实现RS232通信,可以给初学者一个借鉴。-NiosII with 32-bit processors to achieve RS232 communication, can give a reference for beginners.
- 2023-02-24 23:40:03下载
- 积分:1
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add
浮点加法器的用Verilog实现,32位的浮点加法器(Floating point adder Verilog)
- 2021-02-28 12:49:35下载
- 积分:1
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clock_6
ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
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VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的....
VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的.-VHDL state machine design examples, good for the state machine to figure out would be very useful.
- 2022-07-09 03:27:51下载
- 积分:1
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异步FIFO的设计 包括testbench 已调试成功
异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
- 2023-04-13 19:40:03下载
- 积分:1