VHDL 编写的RAM例子

除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助. -Divider can be very good VHDL divider realize the function of great help for beginners.

本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)

The deep lecture notes for basic digital system for cmos design

用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )

说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)

FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)

使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存(Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache)

实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )

自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment

Actel双端口存储；通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示)