VHDL 编写的RAM例子

本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.

ZBT SRAM控制器参考设计，xilinx提供的VHDL源代码-ZBT SRAM controller reference design for Xilinx VHDL source code

96x96 Digital MUX/DEMUX via SPI

xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中(xilinx FPGA design needs DDR2 files that can be applied to the actual design)

Turbo码编解码的FPGA实现，verilog语言编写(Implementation ofTurbo code on FPGA , using Verilog language)

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read

16 bit switch input view in hexa format on 7seg display

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

在Quartus环境下编写，使用Cyclong系列芯片，配置七通道高精度AD5791，该例子为AD5791的FPGA配置使能代码,包括模拟数据输入模块，复位模块，命令接收是能配置模块。(AD5781，Digital signal convert to Analog signal)

开源软核处理器OpenRisc的SOPC设计