是用VHDL语言写的对A/D转换模块的控制程序，希望对大家有帮助。...

控制电话信令 完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)

说明：  verilog编写的RS485读写驱动程序(RS485 read-write driver written by Verilog)

AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23)

GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

generate sine wave. Inputs : Amplitude, phasein, frequency

基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

本程序使用Verilog语言实现了SPI接口的设计，可以直接烧到FPGA实现与MCU的通信,自带有测试文件。(The program uses the Verilog language design SPI interface, you can burn directly communicate with the FPGA, MCU, comes with a test file.)