一个有效的高吞吐量的FPGA的AES实现多千兆位协议

基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter

sub opercore USB CRC5 and CRC16 Modules //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)

this program is a simulation for Aloha

UART communication on SPARTAN 6 it contains tx and rx

Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。

我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)

Its project to move your mouse cursor on a vga monitor. it is very funny -)(Its project to move your mouse cursor on a vga monitor. it is very funny -))