采用VHDL编写的一个简单的UART

altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success

429总线通过FPGA直接实现发送程序,通过Verilog实现(send 429 message by Verilog and FPGA )

数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)

说明：  基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)

verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)

数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.

用FPGA控制1602型液晶显示，显示一行英文语句。(show)

RobustVerilog生成verilog工具(RobustVerilog version)

I2C IP for Quartus V9.0 sp2, can used in SOPC builder.

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)