采用VHDL编写的一个简单的UART

说明：  有关risc-v cpu的问题,里面有一些有关cpu的设计(The problem of risc-v can be solved)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

i2c master ip for altera nios, add in qsys

方案组成模块及系统框图 本方案设计主要由以下模块组成 1：顶层模块 2：数据输入排序模块 3：系统控制模块 4：RAM控制器模块 5：ROM控制器模块 6：蝶型单元模块(Program composition module and system diagram The design of this scheme is mainly composed of the following modules 1: top module 2: data input sorting module 3: system control module 4:RAM controller module 5:ROM controller module 6: butterfly type unit module)

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program

说明：  document qpsk vhdl code

脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器(Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier)

LDPC码不同码率对比，1/2与1/3码率对比。码长512.迭代次数50次。(Comparison of different rate of the LDPC code, 1/2 compared with the 1/3 code rate. 512 yards long. 50 times the number of iterations.)

ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。(ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.)

verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)