采用VHDL编写的一个简单的UART

TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.

sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)

EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals. )

本人上网下载下来并调试过的，完全实现NIOS 下对SD卡读写及包括FAT16文件系统的实现，使用的是QT8.1，FPGA里实现，里面有详细接线图，是完整的一个工程，在EP2C20Q240C8里调试成功-I downloaded off the Internet and debug off, and the full realization of NIOS under the SD card reader and includes FAT16 file system implementation, using QT8.1, FPGA years to achieve, which detailed wiring diagram, is a complete one project in EP2C20Q240C8 debug in the success of

veriloghdl语言熟练的一个很好的cpu代码

说明：  在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)

实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)

8051core-Verilog FPGA

利用matlab、xilinx13.4和ipcorefir编译器5.0进行了低通滤波器的设计。所附的代码将帮助您制作所需频率的低通滤波器。fir编译器有许多不同类型的规范。您可以根据您的要求提供所有规格。这里采样频率为700hz，通带频率为35hz，阻带频率为40hz。在分配完所有的值之后，您可以在matlab中生成滤波器的系数。matlab将生成.coe文件，您可以在FIR编译器中浏览该文件。它将生成一个文件，您可以在ADCU DAC代码中实例化该文件，并获得所需的输出。