采用VHDL编写的一个简单的UART

基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)

AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)

cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)

使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock

一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

使用synopsys的基本步骤，综合工具的使用说明，有用的好东西-Synopsys using the basic steps to use the integrated tools, useful good things

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal