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V2.tar
SDIO slave, written in verilog, does not support SPI mode.
- 2021-04-05 16:59:04下载
- 积分:1
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FPGA基于VHDL的Turbo码
如果本版权声明未从文件中删除,并且任何衍生作品包含原始版权声明和相关免责声明,则可以不受限制地使用和分发本源文件。
- 2022-03-06 11:21:33下载
- 积分:1
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基于FPGA的多功能电子时钟的设计很经典的哦
基于FPGA的多功能电子时钟的设计很经典的哦-FPGA-based multi-functional electronic clock designs are very classic Oh
- 2022-03-21 07:02:37下载
- 积分:1
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MODELSIM的实验程序,在QUARTUSii中调用MODELSIM,实现仿真
MODELSIM的实验程序,在QUARTUSii中调用MODELSIM,实现仿真-ModelSim Experimental procedures QUARTUSii call MODELSIM, realize Simulation
- 2022-04-13 16:01:45下载
- 积分:1
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EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ,经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分:1
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project_1
说明: 简单的一个Verilog小程序,适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分:1
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fir_vivado
此压缩包里面有基于vivado平台的工程,包括了正弦信号的产生,还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of
the generation of the signal of sin and the
design of fir filter and the ari)
- 2016-09-18 15:00:22下载
- 积分:1
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基于fpga的交织编码器设计,主要讲叙如何在fpga上实现交织编码器。...
基于fpga的交织编码器设计,主要讲叙如何在fpga上实现交织编码器。-something about turbo。
- 2023-02-09 02:35:04下载
- 积分:1
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Altera-LVDS_IP
自己总结的Altera_LVDS的IP核的设计及仿真分析,已在实际工程中应用到,并且带有源代码和仿真代码,总结的文档,非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
- 2020-12-16 14:39:13下载
- 积分:1
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基于FPGA,实现了移位除法的功能,程序接口简单,十分好用,已经验证。...
基于FPGA,实现了移位除法的功能,程序接口简单,十分好用,已经验证。-Based on the FPGA, to achieve the division of functional shift, the program interface is simple, very easy to use, has already been verified.
- 2022-10-14 07:10:02下载
- 积分:1