本代码实现了全加器功能，适合初学者学习

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)vhdl

fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz

VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...

基于verilog convolutional coding 的卷积编码(verilog convolutional coding )

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

Universal Shift Register

2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)

USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents

quartusII的使用说明书，特别适用于初学者使用。-quartusII the use of brochures, especially for beginners to use.