多人抢答器 源代码 实用 课程设计 用用VHDL语言

基于VHDL的电子秒表的设计，使用VHDL语言描述一个秒表电路，利用QuantusII软件进行源程序设计，编译，仿真，最后形成下载文件下载至装有FPGA芯片的实验箱，进行硬件测试，要求实现秒表功能。(Design of electronic stopwatch based on VHDL)

MATLAB to HDL Code conversion

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

8级cordic 算法verilog (8 cordic algorithm verilog)

CSC RGB2YUV Verilog source code

本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn

GMSK的调制解调，理理想信道，画出其功率谱。 (GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)

用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有 -Use VHDL to realize the digital frequency synthesis technology, almost the whole of, all have

是基于FPGA的5620的数模转换芯片底层的应用程序，希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)

VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)