hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…

vhdl code for carry lookahead addder

IS611v25616在NIOS II 下的驱动-NIOS II in IS611v25616 under the driver

8对于输入密码锁的键，假设重置后七个灯显示" 0"，并且使用sw1、sw2、sw3 3，只需按任意sw1、sw2、sw3，将使七个灯显示值相加" 1

1、 利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、 利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、 输出波形要求： 在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz； 在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、 通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.

用FPGA实现的模糊控制器 部分用VHDL编写的源程序-Using FPGA to achieve some of the fuzzy controller using VHDL source code prepared

用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。 (Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)

用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特(Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits)

用case 语句描述的4 选1 Mux 源码程序，好用(-4 with a case statement described 1 Mux source program, easy to use)

NN CONTROLLER FOR UPQC

32bit floating point addition