用Bresenham算法在FPGA上实现小数分频器，verilog编写，计算机图形法...

8*8键盘矩阵 用作单片机 8*8键盘矩阵 用作单片机 8*8键盘矩阵 用作单片机-8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a MCU

stratixIVGX，芯片4sgx230es，SDI测试完整工程，实现SDI的收发(stratixIVGX，SDI Receive and Transmit)

一個紅外線感測電路的設計，是經由opa來設計。(An infrared sensing circuit design, is designed by opa.)

FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)

niosII的ip核的实现原理讲解，讲解的非常详细。(niosII ip nuclear realization of the principle of explanation, to explain in great detail.)

通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)

least mean square algo implemented on verilog

彩灯控制器 vhdl语言开发 eda实验-Lantern controller vhdl language test eda

SPI接口协议，将spi总线转换成为LOCALBUS总线(SPI interface protocol, the spi bus converted into LOCAL BUS bus)