以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。...

LDPC码不同码率对比，1/2与1/3码率对比。码长512.迭代次数50次。(Comparison of different rate of the LDPC code, 1/2 compared with the 1/3 code rate. 512 yards long. 50 times the number of iterations.)

FFT with fix point 2*N

8位加法器源代码，vivado实现编写。(8 adder Source, vivado achieve write.)

最近在做毕设，ldpc码的编解码实现，这个是verilog实现。(Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.)

VHDL实例应用的经典，大家学习必看的书籍。-VHDL classic example of the application, see U.S. study books.

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)

说明：  Viterbi译码,IS-95中的1/2码率的卷积码(Viterbi decoding, IS-95 of 1/2 the rate Convolutional Codes)

vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)

ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)

verilog编程语言的讲解，有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)