数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )

以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)

基于CPLD硬件描述语言编写的五电平SVPWM脉冲触发程序(Five level SVPWM pulse trigger program based on CPLD hardware description language)

Quartus环境下多路选择器的编写代码，适合初学数字逻辑设计的进行学习(MUX in Quartus)

Verilog版的C51核(DW8051)-Verilog version of the C51 core (DW8051)

说明：  document qpsk vhdl code

DAC0832的Verilog代码，适用于与ADC0809同时学习，效果明显！(DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!)

TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)