通过VHDL语言的例子，乒乓球运动的FPGA原型样机（2章）是

it will count the bit

GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)

FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)

FPGA SDI 输入，HDMI输出例程(FPGA SDI_IN,HDMI_OUT)

crc32编码的代码(CRC32 coding code)

说明：  IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)

快速付里叶变换子程序所需 RAM 空间以输入的首地址为基址,向增加的方向扩展(Fast Fourier Transform subroutine RAM space required to input the first address of the site was to increase the direction of expansion)

AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)