PCI总线仲裁参考设计，Quicklogic提供的verilog代码

这是一本介绍FPGA设计过程中关键问题的资料书,对参加面试或工程设计有一定帮助-This is an FPGA design process, introduce the key issues of information written on the interview or take part in engineering design has a certain extent, help

大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值-Datang Telecom

四位除法器的VHDL源程序-four division of VHDL source

基于VHDL语言开发的mcu与外部器件的接口程序，解决了高速mcu与低速外部器件的接口问题。-based on VHDL development mcu with external device interface, mcu solve the high-speed and low-speed external device interface.

说明：  VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)

verilog程序设计教程，适合初学者。-verilog programming tutorial for beginners.

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)

这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)

VHDL的初学者可以参考此VHDL加法器，相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest