PCI总线仲裁参考设计，Quicklogic提供的verilog代码

基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)

说明：  该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)

EP1C6_EP1C12核心板原理图，方便自己动手做板学习FPGA-EP1C6_EP1C12 core board schematics, do-it-yourself to do to facilitate learning FPGA board

fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)

用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)

适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.

这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)

verilog编程语言的讲解，有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)

基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)