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ff_const_mul
说明: 常系数有限域乘法器,verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)
- 2011-02-19 21:09:36下载
- 积分:1
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ISPPCBforFPGA
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)
- 2009-12-14 16:55:35下载
- 积分:1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形,但并没有使用ISE内部的FIR滤波器内核,该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分:1
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verilog-learning-of-HuaWei
华为公司学习verilog的资料,绝密资料,想学习verilog编程,想学习FPGA,想以后进华为公司的都可以看看。(Huawei learning verilog information, confidential information, want to learn verilog programming, want to learn FPGA, think later into the Huawei can see.)
- 2013-07-23 14:48:30下载
- 积分:1
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DDS
可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)
- 2020-09-07 15:28:03下载
- 积分:1
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VHDL version of the C8051 core (C8051). Evatronix company s IP core
VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
- 2022-09-22 12:10:03下载
- 积分:1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2023-05-02 18:55:09下载
- 积分:1
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这是用VHDL实现的8位加法器,对新手有点帮助。
这是用VHDL实现的8位加法器,对新手有点帮助。-This is achieved using VHDL adder 8, a little help to novices.
- 2022-07-20 21:54:41下载
- 积分:1
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lic_Xilinx_ISE_Vivado
这是Xilinx ISE 14.X以及vivado、vivado_hls的license,亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)
- 2013-04-26 14:51:09下载
- 积分:1
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在nexys2数字cronometer
该项目是用VHDL编写的,并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止,在按钮0中复位。显示方式与显示方式不同最小:分段到hr:min通过切换开关1
- 2022-11-12 07:55:03下载
- 积分:1