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vhdl
vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)
- 2012-09-23 16:57:41下载
- 积分:1
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Endat2_1_freq
用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)
- 2021-04-26 15:08:45下载
- 积分:1
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VHDL development of the baseball game, in QuartusII environment compiler, apply...
用VHDL开发的棒球游戏,可以在QuartusII环境下编译,适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.
- 2023-04-04 12:25:03下载
- 积分:1
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xilinx-timing-constrains
ISE时序约束笔记——Global Timing Constraints,这个文档中详细介绍了如何使用ISE中约束工具和原理,对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)
- 2012-04-16 11:08:45下载
- 积分:1
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- 2022-12-14 10:50:03下载
- 积分:1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分:1
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SPI_DAC
使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)
- 2011-10-23 21:14:45下载
- 积分:1
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pj_gtx
利用高速口GTX进行快速的数据传输,包括接受和发送模块,用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)
- 2019-03-25 21:40:10下载
- 积分:1
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正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2023-07-26 10:55:02下载
- 积分:1
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e1framerdeframer
E1成帧器和解帧器的FPGA实现源码,测试可用(E1 Framer deframer)
- 2012-12-07 12:10:06下载
- 积分:1