大唐电信的FPGA设计经验，内部资料，详细完整，很有参考价值...

这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use

这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程，程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem )

XCZ7035的硬件平台使用说明 包括USB接口(XCZ7035 hardware platform instructions Including USB interface)

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)

使用uaf42设计的有源滤波器，高通滤波器的设计参数记录(Using uaf42 design active filters, high-pass filter design parameters recorded)

JESD204协议简单透彻的讲解，对做高速AD的朋友有一定的帮助(Understanding control characters in JESD204)

动态获取CPU使用率源码 可以加到压力测试里(Dynamic access to CPU use the source code )

三种方法编写多路选择器的VHDL源代码 分别使用if else ,select ,when 语句-three methods to prepare multiple choice of VHDL source code were used if else, select, when words

说明：  Giao tiep Univesan ...