verilog程序设计教程，适合初学者。

这是一个版本的mp3播放器的迷你尺寸，你可以把它与AVR编程非常easy.it在这个项目这么简单，你使用的fat通过MMC的SPI总线，该总线使主从位置发送数据，然后用此主从，你可以从VS1003发送数据到你的ATmega8然后有一个非常简单的项目。

说明：  能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

在FPGA开发板上用VHDL语言实现了贪吃蛇游戏，开发软件为quartus 2.这是详细的实验报告，包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)

---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.--------- ---- WISHBONE Wishbone_BFM IP Core---- -------- ---- This file is part of the Wishbone_BFM project---- ---- http://www.opencores.org/cores/Wishbone_BFM/---- -------- ---- Description---- ---- Implementation of Wishbone_BFM IP core according to---- ---- Wishbone_BFM IP core specification document.

轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)

USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发，是一个不错的源码。-USB interface controller reference design VHDL code, facilitate the development of FPGA personnel USB development, is a good source.

利用VHDL语言实现PID控制,已经过调试验证。(Using VHDL language to implement PID control)

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

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梁祝音乐verilog code --适用于QUATUS II 开发环境下，适合于verilog入门学员(the verilog code of liangzhu )