verilog程序设计教程，适合初学者。

采用FPGA实现的DDS波形发生器源码，可以实现频率幅值变换、正弦波、方波、三角波输出，输出频率可达1MHz(FPGA implementation of the DDS waveform generator source frequency amplitude transform, sine wave, square wave, triangle wave output, the output frequency up to 1MHz)

分数阶Unscented卡尔曼滤波器研究.pdf(Fractional Unscented Kalman filter pdf)

项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。

hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )

代码用两种方法设计了一个基于多相滤波的内插器，低通滤波器采用128阶凯撒窗，内插倍数32，并且给定信号范围，验证了内插器的正确性，画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )

32位存储器Verilog附带test文件，可以在modulesim仿真 还有加法、减法器，译码器等常用Verilog器件，都附带仿真test。(Memory test with Verilog)

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.

class diagram diagram for AIRS

EDA应用中RAM具体定义实例，供大家学习和写程序参考之用-EDA applications, examples of the specific definition of RAM, for everyone to learn and write programs for reference