verilog程序设计教程，适合初学者。

this come from alter ,you can look and find it on line about jtag.

维特比译码，卷积编码，verilog编写，2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding )

基于FPGA的视频图像加密系统 DE2_70+TRDB—D5M+VGA(FPGA-based video encryption system DE2_70+TRDB-D5M+VGA)

tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master

这是个的VHDL点亮LED的程序，大家一齐分享吧-This is a LED light up the VHDL procedure, let everyone together to share

FPGA简单VGA彩条显示程序驱动程序640*480(FPGA simple VGA color display Driver 640* 480)

这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen

Comparador de magnitud

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)