verilog程序设计教程，适合初学者。

程序来自《现代通信系统－使用matlab》英文版 已经调通！并加上了注释。 希望对大家有帮助1(fpga)

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)

matlab code for communication

altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板(altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board)

VHDL基本运算，采用8位为乘法器，将两个8位字符串的值输入相乘后

可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)

fpga模拟两路视频，简单拼接后，经过GPIF II接口传出给cy2014，测试usb的吞吐量(fpga generate two lane video, and transmit them through GPIF II interface. test cy2014)

说明：  this code works with spi and uart interfaces.

飞思卡尔智能车芯片模块程序 MC9S12XS128 测试通过(freescale smart car for MC9S12XS128)