verilog程序设计教程，适合初学者。

该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)

使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

LCD图形显示代码，已调试过，可以运行成功(LCD graphics display code has been debugged, you can run successfully)

用汇编语言设计的频率计，注释较详细，适于初学者学习使用(Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use)

在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow

嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl

UVM 1.2 golden code, (code for UVM, )

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

NIOS II IDE 编程， FLASH测试程序，仅供参考。-NIOS II programming IDE, FLASH testing procedures, for information purposes only.

AD7606采集代码，用于verilog 驱动 AD7606 adc SPI 串口方式(AD7606 acquisition code, used for Verilog drive AD7606 ADC SPI serial mode)