这是一本介绍FPGA设计过程中关键问题的资料书,对参加面试或工程设计有一定帮助

processor design istruction load pipeline ,hazard

说明：  通过四个半加器的互联，来实现四位加法器的电路结构(Through the interconnection of four and a half adder to achieve the four adder circuit)

dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)

此程序描述了数字电路中与门的逻辑功能。所采取的硬件描述语言为VHDL。程序结构采用了dataflow的写法。请大家仔细阅读。本程序已通过了Altera quartus的验证。确保准确无误。

Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions

interruption routine for PIC16F877

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)

说明：  Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)