这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列...

用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)

快速实现HDB3码与普通码二进制码的转换，方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

VHDL实用教程，详细介绍VHDL语法、开发环境、应用实例等。。。(VHDL course)

使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。(Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.)

此代码是用于旋转一个步进电机所需的方向。

ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)

中文版DLX流水线技术相关方面介绍以及简单应用 适用于面对初学者讲解(Chinese version of the DLX pipeline technology-related aspects of introduction and a simple application Suitable for beginners to explain face)

Verilog，编写的udp收发程序，开发环境xilinx(Verilog, written UDP transceiver)